Semiconductor light emitting device and manufacturing method thereof

ABSTRACT

In semiconductor light emitting sections capable of effectively improving electric cross-talk and effectively avoiding short-circuit between each of light emitting devices, in which a plurality of semiconductor light emitting sections are formed to a semiconductor substrate, and at least one of electrodes for the semiconductor light emitting sections and bonding pads lead out electrically from the electrodes and connected with external leads are formed on one main surface of a semiconductor substrate, a high resistance isolation region is formed, facing the main surface of the semiconductor substrate, below a portion between adjacent conductor layers for electrical leading from the electrode to the bonding pad.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention concerns a semiconductor light emitting device suitable to application, for example, to a multi-beam semiconductor laser device or a multi-beam semiconductor diode device, as well as a manufacturing method thereof.

[0003] 2. Description of Related Art

[0004] A semiconductor light emitting device such as a semiconductor laser or a semiconductor light emitting diode has been used, for example, as an optical device for conducting recording and/or reproduction to an optical recording medium such as an optical disc, or as a light source for a laser beam printer or the like. In recent years, a demand for a multi-beam arrangement has been increased more and more for driving a plurality of light emitting sections independently of each other, for enabling recording and/or reproduction or printing at a higher speed by using such semiconductor light emitting devices.

[0005] On the other hand, for attaining cost reduction and attaining increased speed, it is necessary to reduce the size of an optical system to the multi-beam semiconductor light emitting device and, correspondingly, a demand has been increased for higher degree of integration so as to narrow the beam pitch as much as possible.

[0006] In a semiconductor light emitting device, for example, a semiconductor multi-beam laser for enabling independent driving and intended for higher integration degree, as shown in a schematic perspective view of FIG. 9, a plurality of semiconductor light emitting sections, namely, four semiconductor laser devices M₁ to M₄ in the illustrated example are arranged side by side such that they can be driven independently to a semiconductor substrate 21 at least comprising a first clad layer 2, an active layer 3, and a second clad layer 4 on a semiconductor substrate body 1.

[0007] A method of manufacturing the semiconductor light emitting device is to be explained with reference to schematic cross sectional views for each of steps in FIG. 10 to FIG. 13 and a schematic plan view for a portion of steps shown in FIG. 15 and FIG. 16.

[0008] At first, as shown in FIG. 10A, on a semiconductor substrate 1, for example, made of an n-type GaAs, there are epitaxially grown a first clad layer 2 made of an n-type AlGaAs, an active layer 3 made, for example, of an intrinsic AlGaAs and having a smaller band gap compared with the clad layer 2 and a second clad layer 4 made of p-type AlGaAs successively.

[0009] As shown in FIG. 10C and FIG. 14, and with hatched lines in FIG. 14, current block layers 5 are formed being arranged in parallel in a stripe pattern to the second clad layer 4.

[0010] The current block layers 5 are formed on the area between portions for forming the semiconductor light emitting sections M₁ to M₅ described above and the area corresponding to the outer side of both of outer M₁ and M₄ by etching grooves 6 in a stripe pattern respectively as shown in FIG. 10B.

[0011] Subsequently, an n-type GaAs semiconductor layer of a conduction type different from the second clad layer 4 is epitaxially grown entirely so as to bury the inside of the grooves 6 although not illustrated and etched entirely from the surface thereof to form current block layers 5 formed by leaving the n-type GaAs semiconductor layer only in the grooves as shown in FIG. 10C and FIG. 14.

[0012] As shown in FIG. 12A, a cap layer 7 made of a p-type GaAs of a conduction type identical with that of the second clad layer is epitaxially grown entirely covering the current block layers 5 to constitute a semiconductor substrate 21.

[0013] As shown in FIG. 11B, electrodes isolated from each other, four electrodes in the illustrated example, first to fourth electrodes A₁ to A₄ are deposited in ohmic contact as anode electrodes in this example on the cap layer 7 between each of adjacent current block layers 5. In this case, the electrodes A₁ and A₄ on both sides, a portion thereof is extended to the outside in an L-shaped pattern.

[0014] As shown in FIG. 11C and FIG. 15, an isolation groove 8 is formed between each of the electrodes A₁ to A₄ (indicated by hatched lines in FIG. 15) from the cap layer 7 to a thickness at least traversing the active layer 3.

[0015] As shown in FIG. 12A, an interlayer insulation layer 9 is formed over the entire surface by a CVD (Chemical Vapor Deposition) method.

[0016] As shown in FIG. 12B, first to fourth openings 9W₁ to 9W₄ are perforated on the electrodes A₁ to A₄, respectively, to the interlayer insulation layer 9 (only the first and fourth openings 9W₁ and 9W₄ are disclosed in the cross section of FIG. 12B).

[0017] As shown in FIG. 12C, a flattening insulation material 10 is coated over the entire surface so as to bury the inside of each of the isolation grooves 8.

[0018] Subsequently, as shown in FIG. 13 and FIG. 16, the first to fourth openings 9W₁-9W₂ are opened again to the flattening insulation material 10 from the surface thereof and are etched back in a plane manner to the position that the first to fourth electrodes A₁ to A₂ are exposed to the outside through the openings 9W₁ -9W₄.

[0019] Then, as shown in FIG. 9, conductor layers L₂ and L₃ in ohmic contact with the second and third electrodes A₂ and A₃ respectively through the second and the third openings 9W₂ and 9W₃ are extended and formed overriding the interlayer insulation layers 9, bonding pads PD₂ and PD₃ are constituted at second and third extended ends of the conductor layers L₂ and L₃, and first and fourth bonding pads PD₁ and PD₄ are constituted with the electrodes A₁ and A₄ exposed through the first and fourth openings 9W₁ and 9W₄.

[0020] Although not illustrated, external leads, for example, Au wires are bonded to the bonding pads PD₁ to PD₄ respectively.

[0021] Further, a common counter electrode K, namely, a cathode electrode in the example described above is deposited, for example, in an ohmic contact entirely on the rear face of the semiconductor substrate body 1.

[0022] In this constitution, when driving voltage is applied between each of the anode electrodes A₁ to A₄ and the common cathode electrode K independently, current is supplied restrictively in the stripe portions between the electrodes A₁ to A₄ and the electrode K sandwiched by the current block layers 5 and current is injected restrictively in the active layer 3 below the stripe.

[0023] Opposing end faces 21 m ₁ and 21 m ₂ of the semiconductor substrate 21 constituting both ends of the stripe are formed into a mirror face being constituted, for example, cleavage surface and stripe-like light resonators are constituted in the current injection region between the end faces 21 m ₁ and 21 m ₂ respectively and laser beams are emitted from both end faces. That is, first to fourth semiconductor light emitting sections M₁ to M₄ are constituted in respective portions of the stripes.

[0024] Since the laser devices, that is, the semiconductor light emitting sections M₁ to M₄ are isolated from each other by the isolation grooves 8 and the anode electrodes A₁ to A₄ are constituted electrically independent of each other, they can be driven independently.

[0025] However, as the integration degree is increased in the semiconductor multi-beam laser with the constitution described above, since the distance between each of the laser devices, namely, each of the semiconductor light emitting sections M₁ to M₄ is narrowed, electric cross-talk occurs, actually, between the laser devices, for example, in a case where one of light emitting sections of adjacent laser devices is driven to oscillate continuously, while the other is put to intermittent driving, such that large spike noises occur at the output on the side of the laser device driven to oscillate continuously.

[0026] In the structure, for example, described above, cross-talk is caused greatly by parasitic capacitance formed between portions where the first electrode A₁ and the fourth electrode A₄, and the conductor layers L₂ and L₃ are laminated by way of the interlayer insulation layer 9 and, actually, between opposing ends of the conductor layers L₁ and L₂, and between L₄ and L₃, since they are disposed close to each other.

[0027] As a method of reducing the parasitic capacitance, it has been devised to increase the thickness of the interlay insulation layer 9 or decrease the area of the electrode or the conductor layer laminated on the interlayer insulation layer 9.

[0028] For instance, it has been proposed a structure, as shown in the schematic perspective view of FIG. 17, that the first and fourth electrodes A₁ and A₄ are also arranged in parallel into stripe patterns like the second and third electrodes A₃ and A₂, openings 9W₁ to 9W₄ are apertured respectively to the interlayer insulation layer 9 on each of the electrodes A₁ to A₄, first to fourth conductor layers L₁ to L₄ formed into a narrow width to be in contact therewith are extended on the interlayer insulation layer 9, and bonding pads PD₁ to PD₄ for connection with external leads respectively at the ends thereof are arranged.

[0029] However, also in such a constitution, the cross-talk described above could not be improved effectively. This also depends on that the active layer 3 extends with a large area on both outsides for the light emitting sections M₁ and M₂ on both sides, so that the parasitic capacitance due to the junction capacitance is rather increased.

[0030] In FIG. 17, portions corresponding to those in FIG. 9 carry identical reference numerals, for which duplicate explanations is omitted.

[0031] Further, in each of the constitutions described above, when an accident that interlayer insulation layer is destroyed upon bonding an external lead to the bonding pad by the pressing force, an accident of short-circuiting the light emitting devices tends to occur.

SUMMARY OF THE INVENTION

[0032] An object of the present invention is to effectively improve the electrical cross-talk and effectively avoid short-circuit between the light emitting devices.

[0033] A semiconductor light emitting device according to the present invention has a constitution in which a plurality of semiconductor light emitting sections are formed side by side on a semiconductor substrate, at least one electrode of the semiconductor light emitting sections and a conductor layer led out electrically from each of the electrodes are formed on one main surface of the semiconductor substrate and the conductor layer is formed overriding the interlayer insulation layer on the semiconductor substrate.

[0034] Then, a high resistance isolation region is formed, facing the main surface of the semiconductor substrate, between the semiconductor light emitting sections arranged side by side and on each of the outsides of the light emitting sections disposed on both outsides.

[0035] Further, in the present invention, a high resistance isolation region for partitioning a portion for forming a bonding pad formed to the conductor layer from other portions can be formed on each of the outsides of the semiconductor light emitting sections disposed on both outsides.

[0036] A method of manufacturing a semiconductor light emitting device according to the present invention comprises a step of forming a semiconductor substrate on which a plurality of semiconductor light emitting sections are formed side by side, a step of forming one of electrodes to the semiconductor light emitting sections on one main surface of the semiconductor substrate, a step of forming a conductor layer electrically led out of the electrode on one main surface of the semiconductor substrate and a step of forming, to the semiconductor substrate, a high resistance isolation region, facing the main surface of the semiconductor substrate, between portions for forming each of the semiconductor light emitting sections and to both outsides of the portions for forming the semiconductor light emitting sections.

[0037] In the semiconductor light emitting device according to the constitution of the present invention as described above, since the high resistance isolation region is disposed for all of the plurality of semiconductor light emitting sections, not only between each of the semiconductor light emitting sections but also to the outsides of the semiconductor light emitting sections disposed on both outsides, it is possible to electrically isolate the semiconductor light emitting sections respectively from others, and the parasitic capacitance formed not only between each of the semiconductor light emitting sections but also between the semiconductor light emitting sections disposed on both outsides and the conductor layer of other semiconductor light emitting sections can be reduced and by making the dielectric constant lower, and the cross-talk occurring between the semiconductor light emitting sections caused by the parasitic capacitance can be reduced.

[0038] Further, since the extended portions of the active layer present on both outsides are isolated from the semiconductor light emitting sections present on both outsides, the parasitic capacitance due to the junction capacitance in the semiconductor light emitting sections can also be eliminated.

[0039] Furthermore, as described above, even when the interlayer insulation layer is broken, for example, upon bonding external bonding pads, short-circuits accident between each of the semiconductor light emitting sections can be avoided by separating the bonding pads of the conductor layer disposed in adjacent with each other by the high resistance isolation region from each other.

[0040] Further, in the method of manufacturing the semiconductor light emitting device according to the present invention, the high resistance isolation region is formed also to the outside of the semiconductor light emitting section situated on both outsides of a plurality of semiconductor light emitting sections and, since the high resistance isolation region can be formed simultaneously with the isolation regions for isolating the adjacent light emitting sections from each other, increase in the number of manufacturing steps can be avoided.

[0041] In this text, the semiconductor substrate designates not only the substrate constituted entirely with a semiconductor but also includes a substrate in which a semiconductor layer is formed on an insulative or semi-insulative substrate.

BRIEF DESCRIPTION OF THE DRAWINGS

[0042]FIG. 1 is a schematic plan view of one embodiment for a semiconductor light emitting device according to the present invention;

[0043]FIG. 2 is a schematic cross sectional view taken along line II-II in FIG. 1;

[0044]FIG. 3 is a schematic plan view of another embodiment for a semiconductor light emitting device according to the present invention;

[0045]FIG. 4 is a schematic cross sectional view taken along line IV-IV in FIG. 1;

[0046]FIG. 5A and FIG. 5B are a schematic plan view for one manufacturing step in one embodiment for a semiconductor light emitting device according to the present invention and a schematic cross sectional taken along line B-B thereof;

[0047]FIG. 6A and FIG. 6B are a schematic plan view in one manufacturing step of one embodiment for a semiconductor light emitting device according to the present invention and a schematic cross sectional view taken along line B-B thereof;

[0048]FIG. 7A and FIG. 7B are a schematic plan view in one manufacturing step of one embodiment for a semiconductor light emitting device according to the present invention and a schematic cross sectional view taken along line B-B thereof;

[0049]FIG. 5A and FIG. 5B are a schematic plan view in one manufacturing step of one embodiment for a semiconductor light emitting device according to the present invention and a schematic cross sectional view taken along line B-B thereof;

[0050]FIG. 9 is a schematic perspective view of a n existent semiconductor light emitting device;

[0051]FIG. 10A to FIG. 10C are schematic cross sectional views in each of steps for an existent method of manufacturing a semiconductor light emitting device;

[0052]FIG. 11A to FIG. 11C are schematic cross sectional views in each of steps for an existent method of manufacturing a semiconductor light emitting device;

[0053]FIG. 12A to FIG. 12C are schematic cross sectional views in each of steps for an existent method of manufacturing a semiconductor light emitting device;

[0054]FIG. 13 is a schematic cross sectional view in one step of existent method of manufacturing a semiconductor light emitting device;

[0055]FIG. 14 is a schematic plan view of FIG. 10C;

[0056]FIG. 15 is a schematic plan view of FIG. 11C; and

[0057]FIG. 16 is a schematic plan view of FIG. 12B.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Semiconductor Light Emitting Device

[0058] An example of a preferred embodiment of a semiconductor light emitting device according to the present invention is to be explained with reference to a schematic plan view of FIG. 1 and FIG. 2 illustrating a schematic cross sectional view taken on line II-II in FIG. 1.

[0059] In the semiconductor light emitting device according to the present invention, a plurality of semiconductor light emitting sections, namely, four first to fourth semiconductor light emitting sections M₁ to M₄ in the illustrated embodiment are formed side by side on a semiconductor substrate 21, and first to fourth electrodes A₁ to A₄ for at least one of the semiconductor light emitting sections M₁ to M₄ and conductor layers L₁ to L₄ electrically led out of the first to fourth electrodes A₁ to A₄ are formed by way of an interlayer insulation layer 9 on one main surface 21 a of the semiconductor substrate 21.

[0060] Each of the conductor layers L₁ to L₄ is formed in a narrow width, in the direction crossing, for example, crossing at a light angle to the direction of the stripe for each of the semiconductor light emitting sections M₁ to M₄ and extended to the outside from the portion for forming entire semiconductor light emitting sections M₁ to M₄. For instance, the lateral size for each of the ends is increased to form first to fourth bonding pads PD₁ to PD₄ to be bonded with not illustrated external leads, for example, gold (Au) lead wires by hot press bonding.

[0061] Then, high resistance isolation regions 22 are formed facing the main surface 21a of the semiconductor substrate 21, between each of the semiconductor light emitting sections M₁ and M₂, between M₂ and M₃ and between M₃ and M₄ arranged side by side in plurality and, further, on both outsides of the semiconductor light emitting sections M₁ and M₄ situated on both sides of the semiconductor light emitting sections arranged in plurality, over the entire longitudinal direction of the stripes for the semiconductor light emitting sections M₁ to M₄, respectively.

[0062] Further, a partitioning high resistor isolation regions 22D are disposed further to the outside of the high resistance isolation regions 22 formed to the outside of the outer semiconductor light emitting sections M₁ and M₄, for surrounding the bonding pads PD₁ to PD₂ formed to the conductor layers L₃ and L₄ of the semiconductor light emitting sections M₁ and M₄ and partitioning them from each other, particularly, for partitioning adjacent bonding pads from each other.

[0063] The high resistance isolation region 22D is formed, for example, into a T-shaped pattern comprising a first portion 22D_(A) extended in parallel with the direction of the stripe and a second portion 22D_(B) in perpendicular thereto, which defines first and second partitioning regions S₁ and S₂ forming adjacent bonding pads PD₁ and PD₂, and third and fourth partitioning areas S₃ and S₄ forming the bonding pads PD₃ and PD₄ respectively. The defined area surrounds the portion for forming each of the bonding pads by the partitioning high resistor isolation regions 22D and the edge of the semiconductor substrate constituting the multi-semiconductor laser.

[0064] In another embodiment of the semiconductor light emitting device according to the present invention, the partitioning high resistor isolation region 22D for partitioning the bonding pads and the high resistance isolation region 22 disposed to the outside of the outer semiconductor light emitting section are integrated. FIG. 3 shows a schematic plan view for one embodiment thereof and FIG. 4 shows a schematic cross sectional view taken along line II-II in FIG. 3. However, the invention is not restricted also in this case only to this embodiment.

[0065] In FIG. 3 and FIG. 4, those portions corresponding to those in FIG. 1 and FIG. 2 carry the same reference numerals for which duplicate explanation is to be omitted.

[0066] In this embodiment, high resistance isolation regions 22 are disposed to the outside and along the semiconductor light emitting sections M₁ and M₄ disposed at the outermost sides and they are used also as the first portion 22D_(A) of the partitioning high resistance isolation region 22D in FIG. 1, which is extended therefrom further side way to form the second portion 22D_(B) into a T-shaped pattern.

[0067] In this way, they are constituted so as to function both as the high resistance isolation region 22 formed to the outside of the semiconductor light emitting sections M₁ and M₄ disposed at the outermost side in FIG. 1 and FIG. 2 and the high resistance isolation region 22D for partitioning the bonding pads.

[0068] In each of the embodiments and each of the examples described above, the semiconductor light emitting sections (M₁ to M₄) can be constituted, for example, with semiconductor laser devices.

[0069] As shown, for example, in FIG. 2 and FIG. 4, the semiconductor substrate 21 comprises, formed on a substrate 1 of a first conduction type, for example, n-type GaAs, a first clad layer 2 of an identical conduction type, for example, n-type Al_(0.45)Ga_(0.55)As, an intrinsic active layer 3, for example, of Al_(0.14)Ga_(0.86)As with a smaller band gap, a second conduction type second clad layer 4, for example, of p-type Al_(0.45)Ga_(0.55)As, a first conduction type current block layer 5, for example, of n-type GaAs formed with a stripe-like opening to form a stripe-like current channel, and a second conduction type, for example, p-type GaAs.

[0070] Each of the high resistance isolation regions 22 and 22D is formed from the main surface 21 a of the semiconductor substrate 21 to a depth traversing the active layer 3.

[0071] Each of the high resistance isolation regions 22 and 22D can be constituted such that an isolation groove 23 is formed from the main surface 21 a of the semiconductor substrate 21, for example, to such a depth as traversing the active layer 3, an insulation layer 24 such as SiO₂ or SiN is formed to the inner surface thereof, and a flattening material 25 made of an insulative resin material having a relatively low dielectric constant is buried into a concave of the isolation groove 23 for making a flat surface which is just in flush with other surfaces.

[0072] Further, each of the high resistance isolation regions 22 and 22D can also be constituted as region increased with the resistivity due to crystal damages caused by ion injection although not illustrated.

Method of Manufacturing a Semiconductor Light Emitting Device

[0073] A method of manufacturing a semiconductor light emitting device according to the present invention described above is to be explained. The structure of the semiconductor light emitting device according to the present invention is made more clear by the description for the manufacturing method.

[0074] A method of manufacturing a semiconductor light emitting device according to the present invention shown in FIG. 1 and FIG. 2 is to be explained with reference to FIG. 5 through FIG. 8. In FIG. 5 through FIG. 8, each of the figures A is a schematic plan view for a main portion in each of the steps and each of figures B is a schematic cross sectional view taken along line B-B in each of the figures A.

[0075] As shown in FIG. 5A and FIG. 5B, a semiconductor substrate 21 is constituted and first to fourth electrodes Al to A₄ are deposited on one main surface 21 a thereof.

[0076] The semiconductor substrate 21 and the electrodes A₁ to A₄ can be formed by the same procedures as those explained for FIG. 11A through FIG. 10C, and FIG. 1A and FIG. 1B. On a semiconductor substrate 1 comprising, for example, of n-type GaAs, there are epitaxially grown a first clad layer 2 comprising, for example, n-type Al_(0.45)Ga_(0.55)As, an intrinsic active layer 3 comprising, for example, of non-doped Al_(0.14)Ga_(0.86)As and a second clad layer 4 comprising p-type Al_(0.45)Ga_(0.55)As successively by an MOCVD (Metal Organic Chemical Vapor Deposition) method.

[0077] Then, current block layers 5 each having a stripe-shaped opening 5W in parallel with each other on the second clad layer 4 are formed to the portions for forming the semiconductor emitting sections respectively.

[0078] Upon forming the current block layers 5, as explained with reference to FIG. 10B, grooves 6 are formed respectively, for example, by RIE (Reactive Ion Etching) to portions for selectively forming the current block layers 5 in a stripe patterns, that is, between the portions for forming each of the semiconductor light emitting sections and to the outside of the portions for forming the semiconductor light emitting sections formed to the outermost side, for example, over the entire area in this embodiment. Subsequently, an n-type GaAs semiconductor layer having a conduction type different from that of the second clad layer 4 is epitaxially grown entirely so as to bury the inside of the grooves 6 and etching is applied entirely from the surface to form the current block layer 5 while leaving the n-type GaAs semiconductor layer only in the grooves 6.

[0079] Further, as explained with reference to FIG. 11A, a cap layer 7 comprising p-type GaAs is epitaxially grown covering the current block layers 5, for example, by MOCVD.

[0080] The semiconductor substrate 21 is constituted in this way.

[0081] The active layer 3 is formed to the semiconductor substrate 21 at such a level that the depth from the main surface 21 a of the semiconductor substrate 21 formed with the surface of the cap layer 7 is about 1.5 to 2.5 μm and the thickness of the active layer can be made, for example, to about 0.1 μm.

[0082] Then, corresponding to the stripe-shaped openings 5W of the current block layers 5, stripe-shaped first to fourth electrodes A₁ to A₄ are deposited in parallel in ohmic contact, respectively, along the openings 5W on the cap layer 7 facing the main surface 21 a of the semiconductor substrate 21 as shown in FIG. 5.

[0083] Then, as shown in FIGS. 6A and 6B, an isolation groove 23 is formed between each of the electrodes A₁ to A₄ and to the outside of the electrodes A₁ and A₄ on both outer sides in parallel with the electrodes A₁ to A₄, and a partitioning isolation groove 23D in a T-shaped pattern is formed further to the outside thereof. Each of the isolation grooves 23D comprises a first part 23D_(A) in parallel with the stripe-like isolation groove 23 and a part section 23D_(B) in perpendicular thereto, and the T-shaped isolation grooves 23D define two partitioned areas S₁ and S₂, and S₃ and S₄ respectively.

[0084] The isolation grooves 23 and 23D can be formed, for example, by RIE. Further, the depth of the isolation grooves 23 and 23D is made to such a depth as traversing the active layer 3, for example, of about 3.5 to 5.0 μm, and the width for the isolation grooves 23 and 23D is selected, for example, as about from 2 to 5 μm so as to provide an aspect ratio as capable of preferably forming the insulation layer and filling the flattening material to the inner surface of the isolation groove to be described later.

[0085] Then, as shown in FIG. 7A and FIG. 7B, an insulation layer 24 such as made of SiN or SiO₂ is formed entirely to a thickness, for example, of about 300 nm once by a method capable of depositing the same to the inner surface of each of the isolation grooves 23 and 23D with good coverage such as CVD (Chemical Vapor Deposition) method or sputtering. Subsequently, first to fourth openings 24W₁ to 24W₄ are apertured by a well-known pattern etching on each of the stripe-like shape electrodes A₁ to A₄ respectively.

[0086] In this case, the openings 24W₁ to 24W₄ are preferably positioned corresponding respectively to partition areas S₁ to S₄.

[0087] Then, as shown in FIGS. 8A and 8B, a flattening material 25 with low dielectric constant and having insulative property is formed so as to bury the inside of each of the isolation grooves 23 and 23D. The flattening material 25 is formed by once forming a polyimide resin or the like entirely by rotational coating to such a thickness as flattening the surface, subsequently, re-opening each of the first to fourth openings 24W₁ to 24W₄, for example, by mechano-chemical polishing, and etching back the flattening material 25 from the surface in a plane manner to a position where each of the first to fourth electrodes A₁ to A₄ are exposed to the outside through the openings 24W₁ to 24W₄.

[0088] In this constitution, an interlayer insulation layer 9 is constituted with the insulation layer 24 and the flattening material 25.

[0089] Then, as shown in FIG. 1 and FIG. 2, conductor layers L₁ to L₄ in ohmic contact respectively with the first to fourth electrodes A₁ to A₄ through each of the first to fourth openings 24W₁ to 24W₄ are extended on each of the first to fourth partitioned areas S₁ to S₄ overriding the interlayer insulation layer 9 comprising the insulation layer 24 and the flattening material 25. The width of each of the conductor layers L₁ to L₄ is enlarged in the extended portion on each of the first to fourth partitioned areas S₁ to S₄ to form first to fourth bonding pads PD₁ to PD₄ respectively.

[0090] Further, a common counter electrode, a cathode electrode K in this embodiment, is deposited in ohmic contact, for example, entirely to the rear face of the semiconductor substrate 1.

[0091] Then, the end face for each of the stripe portions for each of the semiconductor emitting sections M₁ to M₄ is made as a mirror surface by constituting the same with cleavage surface.

[0092] The semiconductor light emitting device explained with reference to FIG. 1 and FIG. 2 is constituted by the method described above. In this constitution, when predetermined voltage is applied between each of the anode electrodes A₁ to A₄ and the common cathode electrode K, a current is charged restrictively to the active layer 3 below a stripe portion put between the current block layers 5 between the electrodes A₁ to A₄ and K, to constitute to semiconductor light emitting sections M₁ to M₄ comprising light resonators with the longitudinal direction of the stripe being as the longitudinal direction of the resonator, that is, semiconductor laser devices in this embodiment respectively, and laser light is emitted forwardly and backwardly from both end faces of each of the light resonators.

[0093] Then, since the laser devices, that is, the semiconductor light emitting sections M₁ to M₄ are electrically isolated from each other by the high resistance isolation regions 22 comprising the insulation layer 22 and the flattening material 25 formed in the isolation grooves 23 and the respective anode electrodes A₁ to A₄ are independently constituted electrically, each of the devices can be driven independently of each other.

[0094] Then, in the semiconductor light emitting device of this structure, the high resistance isolation region 22 is disposed with respect to each of the semiconductor light emitting sections M₁ to M₂, that is, not only between each of the semiconductor light emitting sections but also to the outside of the semiconductor light emitting sections M₁ and M₄ disposed to both outsides to isolate the semiconductor light emitting sections electrically from each other, and the high resistance isolation region 22 can be constituted to have a low dielectric constant, so that it is possible to reduce the parasitic capacitance formed not only between each of the semiconductor light emitting sections but also relative to the conductor layers L₃ and L₄ for other semiconductor light emitting sections and, particularly, between the bonding pads and, accordingly, cross-talk occurring between the semiconductor light emitting sections caused by the parasitic capacitance can be decreased.

[0095] Further, in the semiconductor light emitting sections M₁ and M₄ on both outsides, since the active layer extending to the outside thereof is isolated, the junction capacitance of the active layer extended to the outside thereof can be eliminated.

[0096] Further, as described above, since the conductor layers between the bonding pads disposed being adjacent with each other are partitioned by the partitioning high resistor isolation region 22D, even if the interlayer insulation layer 9 is fractured, for example, upon bonding of an external lead to the bonding pad, it is possible to avoid short-circuit accident between semiconductor light emitting sections to each other.

[0097] Further, in the method of manufacturing the semiconductor light emitting device according to the present invention, the high resistance isolation region 22 and the partitioning high resistance isolation region 22D are formed also to the outside of the semiconductor light emitting sections situated on both outsides of a plurality of semiconductor light emitting sections but, since the high resistance isolation regions can be formed simultaneously with the isolation regions for isolating adjacent light emitting sections from each other, increase for the number of steps can be avoided.

[0098] For the manufacturing method according to the present invention described above, explanation has been made to a case of obtaining the structure shown in FIG. 1 and FIG. 2, but the semiconductor light emitting device with the constitution shown in FIG. 3 and FIG. 4 can also be manufactured by the same procedures as those in FIG. 5 to FIG. 8 described previously, excepting that the high resistance isolation regions at the outside of the high resistance isolation regions 22 disposed to the outside of the semiconductor light emitting sections is formed into a pattern integrated with the high resistance isolation region 22D for partitioning the bonding pads from each other.

[0099] Further, the high resistance isolation regions such as the high resistance isolation 22 or the partitioning high resistance isolation region 22D described above can also be formed by damaging crystals entirely or partially by ion implantation to increase the resistance.

[0100] While explanations have been made for each of examples described previously with respect to one multi-beam semiconductor light emitting device, a plurality of semiconductor light emitting devices can be manufactured simultaneously in actual production, by forming a plurality of multi-semiconductor light emitting devices to a single sheet of the semiconductor substrate 21 and then isolating them into each of multi-beam semiconductor light emitting devices.

[0101] In each of the examples described above, four semiconductor light emitting sections M₁ to M₄ are arranged and formed T-shaped patterns for partitioned areas S₁ to S₄ by paired partitioning high resistance isolation regions 22D, but it may be constituted such that an optional number of semiconductor light emitting sections are arranged, in which the partitioning high resistance isolation region 22D can be formed into a pattern of various shapes for partitioning so as to surround each of the bonding pads.

[0102] While the embodiment describes above show the semiconductor light emitting section as the semiconductor laser device but it may be constituted with a semiconductor light emitting diode device.

[0103] Further, the embodiment described above is constituted with AlGaAs series III-V group semiconductor but it may be constituted with various other III-V group semiconductors such as AlGaInAs or AlGaInP, or with II-VI group semiconductors such as ZnMgSSe series, or a so-called SCH (Separate Confinement Hetero structure) in which a guide layer is disposed in adjacent with the active layer.

[0104] In the semiconductor light emitting device according to the present invention, as described above, since the portion between each of the light emitting sections and the portion between the light emitting section and the conductor layer as the lead portion is isolated by the high resistance isolation regions, that is, a low dielectric constant region, capacitance caused by the extended portion on both outsides of the active layer regarding the semiconductor light emitting sections on both outsides can be reduced and cross-talk between them can be avoided effectively and response can be improved, also in a case where the density for the integration degree of the semiconductor light emitting sections is increased in the semiconductor light emitting device.

[0105] Then, by the improvement for the cross-talk, it is possible, in a case where one of adjacent light emitting sections is put to a continuous oscillation driving, while another light emitting section is driven intermittently as described in the preceding part of this text to avoid interference between each other, such as generation of large spike noises to the output of the laser device put to continuous oscillation driving, and stable operation can be conducted.

[0106] Further, since the light emitting section and the conductor layer forming the lead portion are separated from each other by the high resistance isolation region, occurrence of short-circuit accident can be avoided upon assembling operation for the semiconductor light emitting device, for example, in a bonding operation for lead wires such as gold wires by hot press bonding to the bonding pad of the conductor layer of lead portions led out of the electrode of the semiconductor light emitting section even in a case where the interlayer insulation layer below the bonding pad is damaged Accordingly, it is possible to improve the yield and enhance the reliability.

[0107] Further, while the method of manufacturing the semiconductor light emitting device according to the present invention is adapted for obtaining a semiconductor light emitting device of a structure in which not only the semiconductor light emitting sections are isolated from each other but also they are isolated from the portions, the high resistance isolation region for conducting isolation from other portions can be conducted simultaneously with the existent isolation operation, so that it does not increase the number of steps and can avoid disadvantages such as lowering of the productivity and increase of the manufacturing cost. 

What is claimed is:
 1. A semiconductor light emitting device in which a plurality of semiconductor light emitting sections are formed side by side on a semiconductor substrate, at least one electrode of the semiconductor light emitting sections and a conductor layer led out electrically from each of the electrodes are formed on one main surface of the semiconductor substrate and the conductor layer is formed overriding the interlayer insulation layer on the semiconductor substrate, wherein: a high resistance isolation region is formed, facing the main surface of the semiconductor substrate, between the semiconductor light emitting sections arranged side by side and on each of the outsides of the light emitting sections disposed on both outsides.
 2. A semiconductor light emitting device as claimed in claim 1, wherein a high resistance isolation region for partitioning a portion for forming a bonding pad formed to the conductor layer from other portions is formed on each of the outsides of the semiconductor light emitting sections disposed on both outsides.
 3. A semiconductor light emitting device as claimed in claim 1, wherein the semiconductor light emitting section is a semiconductor laser device.
 4. A semiconductor light emitting device as claimed in claim 1, wherein the semiconductor substrate comprises at least a first clad layer, an active layer and a second clad layer and the high resistance isolation region is formed to such a depth from the one main surface of the semiconductor substrate as traversing the active layer.
 5. A semiconductor light emitting device as claimed in claim 1, wherein the high resistance isolation region comprises an isolation groove formed on the semiconductor substrate.
 6. A semiconductor light emitting device as claimed in claim 1, wherein the high resistance isolation region comprises an isolation groove formed on the semiconductor substrate and a flattening material filled in the isolation groove.
 7. A semiconductor light emitting device as claimed in claim 1, wherein the high resistance isolation region comprises an ion implanted high resistance region formed in the semiconductor substrate.
 8. A method of manufacturing a semiconductor light emitting device comprising the steps of: forming a semiconductor substrate on which a plurality of semiconductor light emitting sections are formed side by side; forming one of electrodes to the semiconductor light emitting sections on one main surface of the semiconductor substrate; forming a conductor layer electrically led out of the electrode on one main surface of the semiconductor substrate; and forming, to the semiconductor light emitting device, a high resistance isolation region, facing the main surface of the semiconductor, substrate between a portion for forming each of the semiconductor light emitting sections and to both outsides of the portions for forming the semiconductor light emitting sections.
 9. A method of manufacturing a semiconductor light emitting device as claimed in claim 8, wherein the high resistance isolation region extending between adjacent bonding pads of the bonding pads formed to the conductor layer is formed to the high resistance isolation region formed on both outsides of the portions for forming the semiconductor light emitting sections in the step of forming the high resistance isolation region.
 10. A method of manufacturing a semiconductor light emitting device as claimed in claim 8, wherein the semiconductor light emitting section is a semiconductor laser device.
 11. A method of manufacturing a semiconductor light emitting device as claimed in claim 8, wherein the semiconductor layer comprises at least a first clad layer, an active layer and a second clad layer, and the high resistance isolation region is formed to such a depth as traversing the active layer.
 12. A method of manufacturing a semiconductor light emitting device as claimed in claim 8, wherein the step of forming the high resistance isolation region comprises a step of forming an isolation groove to the semiconductor substrate.
 13. A method of manufacturing a semiconductor light emitting device as claimed in claim 8, wherein the step of forming the high resistance isolation region comprises a step of forming an isolation groove to the semiconductor substrate, and a step of filling a flattening material in the isolation groove.
 14. A method of manufacturing a semiconductor light emitting device as claimed in claim 8, wherein the step of forming the high resistance isolation region comprises an ion implanting step. 